In recent years, shift register (Gate on Array, GOA) technology is widely applied in liquid crystal display panel, hence people have increasingly high requirements to the lifetime of GOA, work consumption of GOA and the work stability of GOA.
In prior art, a circuit structure of one GOA unit is shown with reference to FIG. 1, wherein VDD is a direct current high voltage, so that the eighth thin-film transistor M8 is kept at on-state due to the high voltage of VDD and thus a pull-down node PD point is at high level. Therefore, when PD is at high level state, the sixth thin-film transistor M6 and the fourth thin-film transistor M4 are at on-state. Only when the pull-up node PU point is at high level, the ninth thin-film transistor M9 is turned on, such that the PD point is at low level, thereby the sixth thin-film transistor M6 and the fourth thin-film transistor M4 connected to the pull-down node are cutoff However, as the duration in which the PD node is at high level is much longer than the duration in which the PD node is at low level, the gates of the sixth thin-film transistor M6 and the fourth thin-film transistor M4 connected to the pull-down node are at high level for long time, i.e. at a high duty cycle state, thereby the lifetime of the thin-film transistors is affected.